All modern computer systems have a mechanism for managing the communication of data between the one or more electrical units/components of the computer system. For example, a computer system may include a processor that executes a plurality of instructions in order to perform a function, a memory for storing the instructions currently being executed by the processor as well as data that is acted on by the instructions, a persistent storage device for storing one or more different software programs (each comprising one or more instructions executed by the processor) even when the computer system is powered down and one or more peripheral devices. The peripheral devices may include input/output devices such as a keyboard, a mouse, a printer and other interface controllers to input/output ports. During the normal operation of the computer system, data has to be communicated between the input/output devices or ports and the processor. To alert the processor to the fact that a particular peripheral device has data to communicate, an interrupt signal may be generated by the particular peripheral device. Typically, there may be some interrupt signals that are permanently assigned to a particular peripheral device while other interrupt signals are assigned on a dynamic basis. For example, a keyboard is typically permanently assigned the first interrupt signal (IRQ0) while a universal serial bus (USB) port may be assigned whatever interrupt signal is available when the USB port needs to alert the processor that it needs to communicate data.
In a typical computer system, the interrupt signal generated by a peripheral device is fed to the processor. The processor may, based on the information in the interrupt signal, be directed to a particular interrupt handling/service routine that is stored in the memory of the computer system. Typically, for each different peripheral device or port, there may be a separate interrupt handling routine. The processor may then execute the instructions in the particular interrupt handling routine in order to handle the data communications with the particular peripheral device. This is how the interrupt handling for a typical single processor computer systems works.
The problem with this single processor interrupt handling technique is that it cannot be effectively used for a multiple processor system. In particular, when there are two or more processors in the computer system, the above described interrupt handling system is ineffective for a variety of reasons. First, when there are one or more processors, it is possible that the interrupt handling routine can be handled by either of the processors or the tasks in the interrupt handling routine can be split between the two or more processors. In addition, if one processor is too busy when it receives an interrupt, the interrupt can be redirected to the other processor that has more processing capacity at the particular time that the interrupt has occurred. A typical single processor interrupt handling system cannot effectively handle the interrupt handling process due to the differences that exist between a single processor computer system and a multiple processor computer system. Thus, it is desirable to provide a multiple processor interrupt handling system and method and it is to this end that the present invention is directed.